The present invention relates to decoding a digital audio data stream, and more particularly to decoding a biphase-mark encoded data stream in the digital domain using a software-based frequency locked loop.
Digital audio receivers that receive and decode digital audio data are used in a variety of consumer and professional audio products such as audio/video receivers, DVD players and recorders, and personal video recorders, for example. Several audio interfaces exist to allow different devices to communicate digital audio data with one another. The worldwide audio standard is referred to the as International Electrotechnical Commission 60958 (IEC-60958). Two related standards include the Audio Engineering Society""s AES3 standard, and the Sony/Philips Digital Interface (S/PDIF). One commonality among these standards is that they modulate the signal using biphase-mark encoding (or simply biphase encoding) to transmit digital audio information in serial format.
Biphase-mark encoded standards require that the digital audio data be transmitted in blocks, where each block comprises 192 consecutive frames for each of two channels. FIG. 1 is a diagram illustrating the IEC958 frame format. A frame 10 comprises two sub-frames 12, one for each channel. The rate of transmission of the frames corresponds to the source sampling frequency. Samples of the audio signal are transmitted in two channels, and a receiver is able to extract the clock from the transmitted signal. Each sub-frame 12 is divided into thirty-two time slots for storing data bits. The first four bits form a preamble, the following four bits include auxiliary data, the following twenty bits contain an audio sample, and the last four bits contain control information.
To facilitate clock recovery from the data stream and to minimize the DC component on the transmission line, time slots 4 to 31 are encoded in biphase-mark. Each time slot, which transmits one bit of data, always starts with a transition or edge of the signal and ends with a transition of the signal. Further, each time slot is represented by two consecutive binary states, where the occurrence of a transition in the middle of a given time slot indicates that a xe2x80x9c1xe2x80x9d is encoded, while the absence of a transition in a time slot indicates that a xe2x80x9c0xe2x80x9d is encoded
FIG. 2 illustrates an example of biphase-mark encoding. A clock signal 16 is shown for reference. An example set of source data 18 is shown that is to be encoded, followed by example encoded data 20 after biphase-mark encoding. The example clock rate is twice the data transmission rate. Each bit from the source data 18 is transmitted in the encoded data 20 in a time slot of length T. As shown, xe2x80x9c1sxe2x80x9d in the source data 18 are encoded in the encoded data 20 with transitions occurring at 0.5T, while the xe2x80x9c0sxe2x80x9d have no transition.
Referring again to FIG. 1, the preambles 14 of each sub-frame 12 are specific patterns that provide synchronization and identification of sub-frames 12 and blocks. This allows the receiver to lock onto the data sample within one sub-frame frame 12.
FIG. 3 is a block diagram illustrating the three preambles used to identify the beginning of the sub-frames and blocks; and FIG. 4 shows relative waveforms for the preambles. There are three defined preambles 14: one for each channel and one to indicate the beginning of a channel and a block. The corresponding channel coding for each of the preambles 14 is also shown. Preamble xe2x80x9cBxe2x80x9d represents the beginning of channel A and a block. Preamble xe2x80x9cMxe2x80x9d represents the beginning of channel A only. And preamble xe2x80x9cWxe2x80x9d represents the beginning of channel B. In broadcasting environments, the letters B, M, and W are denoted by Z, X, and Y, respectively.
So that they can be easily identified by the receiver, each preamble 22 contains biphase coding violations, as shown in FIG. 4. Biphase-mark data is required to transition at every time slot, but each preamble 22 violates that requirement twice because each preamble 22 has two time slots, or bit boundaries, with no transitions.
Biphase-mark encoding has the advantage of providing a self-clocking data signal. Conventional digital audio receivers typically include an analog phase-locked loop (PLL) to recover the clock signal from the data signal. The PLL includes a digital edge-triggered phase detector coupled to a voltage-controlled oscillator. Through a feedback loop, the voltage-controlled oscillator is used to generate an independent clock signal having a frequency designed to match the clocking of incoming biphase-mark encoded data signal.
Although conventional digital audio receivers work for their intended purposes, the sampling frequency of incoming digital audio data may change significantly. In addition, the signal may suffer from jitter and noise, making it even more difficult for the digital audio receiver to decode the audio data. Because the PLL""s used in conventional digital audio receivers are analog, these receivers take longer to adapt to the changing input sampling frequency due to low pass filter characteristics. If the digital audio receiver is incapable of keeping up with the changing sampling frequency of the input signal, then unsatisfactory decoding of the digital audio signal will result.
Accordingly, what is needed is an improved method and system for decoding biphase encoded data. The present invention addresses such a need.
The present invention provides a method and system for decoding a biphase-mark encoded input stream. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream to generate decoded data and storing the decoded data in a data buffer; reading, by an audio out module, the decoded data from the data buffer at a rate determined by a programmable clock; using the timing information from the receiver module to calculate a sampling frequency of the input stream; and adjusting the frequency of the programmable clock to substantially match the sampling frequency so that the audio out module reads the decoded data from the buffer at substantially the same rate that the receiver module inputs the decoded data into the data buffer.
According to the method and system disclosed herein, the present invention decodes the biphase input stream entirely in the digital domain using a software-based frequency locked loop, which matches the frequency of the programmable clock with the sampling frequency of the input stream in order to synchronize the audio out module with the receiver module.